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DSPIC33EP128GS708 Datasheet(PDF) 197 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 197 Page - Microchip Technology |
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197 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 197 dsPIC33EPXXXGS70X/80X FAMILY REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64, maximum PWM timing resolution 101 = Divide-by-32, maximum PWM timing resolution 100 = Divide-by-16, maximum PWM timing resolution 011 = Divide-by-8, maximum PWM timing resolution 010 = Divide-by-4, maximum PWM timing resolution 001 = Divide-by-2, maximum PWM timing resolution 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-7: STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER(1,2) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8. 2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a period resolution at 8.32 ns (at fastest auxiliary clock rate). |
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