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DSPIC33EP128GS708 Datasheet(PDF) 198 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 198 Page - Microchip Technology |
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198 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 198 2016-2018 Microchip Technology Inc. REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SSEVTCMP<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 SSEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SSEVTCMP resolution is 8.32 ns. REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled bit 14-10 Unimplemented: Read as ‘0’ bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits Value is in 8.32 ns increments. The frequency of the chop clock signal is given by: Chop Frequency = 1/(16.64 * (CHOP<7:3> + 1) * Primary Master PWM Input Clock Period). bit 2-0 Unimplemented: Read as ‘0’ Note 1: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the PTCON2 register (Register 16-2). |
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