DSPIC33EP128GS708 datasheet(362/484 Pages) MICROCHIP

362 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 362

 2016-2018 Microchip Technology Inc.

The different device security segments are shown in

Figure 27-3. Here, all three segments are shown but

are not required. If only basic code protection is

required, then GS can be enabled independently or

combined with CS, if desired.

FIGURE 27-3:

SECURITY SEGMENTS

EXAMPLE FOR

dsPIC33EPXXXGS70X/80X

DEVICES

dsPIC33EPXXXGS70X/80X family devices can be

operated in Dual Partition mode, where security is

required for each partition. When operating in Dual Par-

tition mode, the Active and Inactive Partitions both

contain unique copies of the Reset vector, Interrupt

Vector Tables (IVT and AIVT, if enabled) and the Flash

Configuration Words. Both partitions have the three

security segments described previously. Code may not

be executed from the Inactive Partition, but it may be

programmed by, and read from, the Active Partition,

subject to defined code protection. Figure 27-4 and

Figure 27-5 show the different security segments for

devices operating in Dual Partition mode.

The device may also operate in a Protected Dual

Partition mode or in Privileged Dual Partition mode. In

Protected Dual Partition mode, Partition 1 is perma-

nently erase/write-protected. This implementation

allows for a “Factory Default” mode, which provides a

fail-safe backup image to be stored in Partition 1. For

example, a fail-safe bootloader can be placed in

Partition 1, along with a fail-safe backup code image,

which can be used or rewritten into Partition 2 in the

event of a failed Flash update to Partition 2.

Privileged Dual Partition mode performs the same

function as Protected Dual Partition mode, except

additional constraints are applied in an effort to prevent

code in the Boot Segment and General Segment from

being used against each other.

FIGURE 27-4:

SECURITY SEGMENTS

EXAMPLE FOR

dsPIC33EP64GS70X/80X

DEVICES (DUAL

PARTITION MODES)

IVT and AIVT

Assume

IVT

AIVT + 256 IW(2)

0x000000

0x000200

BSLIM<12:0>

0x0XXX00

CS(1)

Note 1:

If CS is write-protected, the last page

(GS + CS) of program memory will be

protected from an erase condition.

The last half (256 IW) of the last page of

BS is unusable program memory.

BS Protection

IVT

AIVT + 256IW(2)

CS(1)

Unimplemented

(read ‘0’s)

IVT

AIVT + 256 IW(2)

CS(1)

Note 1:

If CS is write-protected, the last page

(GS + CS) of program memory will be

protected from an erase condition.

The last half (256 IW) of the last page of

BS is unusable program memory.

0x000000

0x000200

BSLIM<12:0>

IVT and AIVT

Assume

IVT and AIVT

Assume

0x005800

0x400000

0x400200

BSLIM<12:0>

0x405800

BS Protection

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