DSPIC33EP128GS708 datasheet(359/484 Pages) MICROCHIP

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DS70005258C-page 359

dsPIC33EPXXXGS70X/80X FAMILY

27.3

User OTP Memory

The dsPIC33EPXXXGS70X/80X family devices contain

64 words of user One-Time-Programmable (OTP) mem-

ory, located at addresses, 0x800F80 through 0x800FFC.

The user OTP Words can be used for storing checksum,

code revisions, product information, such as serial

numbers, system manufacturing dates, manufacturing lot

numbers and other application-specific information.

These words can only be written once at program time

and not at run time; they can be read at run time.

27.4

On-Chip Voltage Regulator

All the dsPIC33EPXXXGS70X/80X family devices power

their core digital logic at a nominal 1.8V. This can create

a conflict for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the dsPIC33EPXXXGS70X/80X

family incorporate an on-chip regulator that allows the

device to run its core logic from VDD.

The regulator provides power to the core from the other

VDD pins. A low-ESR (less than 1 Ohm) capacitor (such

as tantalum or ceramic) must be connected to the VCAP

pin (Figure 27-1). This helps to maintain the stability of

the regulator. The recommended value for the filter

capacitor is provided in Table 30-5, located in

Section 30.0 “Electrical Characteristics”.

FIGURE 27-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1,2,3)

27.5

Brown-out Reset (BOR)

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the reg-

ulated supply voltage, VCAP. The main purpose of the

BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (for

example, missing portions of the AC cycle waveform

due to bad power transmission lines or voltage sags

due to excessive current draw when a large inductive

load is turned on).

A BOR generates a Reset pulse which resets the

device. The BOR selects the clock source based on the

device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an Oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the Power-up Timer (PWRT) Time-out

(TPWRT) is applied before the internal Reset is released.

If TPWRT = 0 and a crystal oscillator is being used, then a

nominal delay of TFSCM is applied. The total delay in this

case is TFSCM. Refer to Parameter SY35 in Table 30-23

of Section 30.0 “Electrical Characteristics” for specific

TFSCM values.

The BOR status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to oper-

ate while in Sleep or Idle modes and resets the device

should VDD fall below the BOR threshold voltage.

Note:

It is important for the low-ESR capacitor to

be placed as close as possible to the VCAP

pin.

Note 1:

These are typical operating voltages. Refer

to Table 30-5 located in Section 30.0

“Electrical Characteristics” for the full

operating ranges of VDD and VCAP.

It is important for the low-ESR capacitor

to be placed as close as possible to the

VCAP pin.

Typical VCAP pin voltage = 1.8V when

VDD ≥ VDDMIN.

VDD

VCAP

VSS

dsPIC33EP

3.3V

CEFC

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