DSPIC33EP128GS708 datasheet(360/484 Pages) MICROCHIP

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dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 360

 2016-2018 Microchip Technology Inc.

27.6

Watchdog Timer (WDT)

For dsPIC33EPXXXGS70X/80X family devices, the

WDT is driven by the LPRC oscillator. When the WDT

is enabled, the clock source is also enabled.

27.6.1

PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration

bit. With a 32 kHz input, the prescaler yields a WDT

Time-out Period (TWDT), as shown in Parameter SY12

in Table 30-23.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>), which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler time-out periods, ranges from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSCx bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

27.6.2

SLEEP AND IDLE MODES

If the WDT is enabled, it continues to run during Sleep or

Idle modes. When the WDT time-out occurs, the device

wakes and code execution continues from where the

PWRSAV instruction was executed. The corresponding

SLEEP or IDLE bit (RCON<3:2>) needs to be cleared in

software after the device wakes up.

27.6.3

ENABLING WDT

The WDT is enabled or disabled by the WDTEN<1:0>

Configuration bits in the FWDT Configuration register.

When the WDTEN<1:0> Configuration bits have been

programmed to ‘0b11’, the WDT is always enabled.

The WDT can be optionally controlled in software

when the WDTEN<1:0> Configuration bits have been

programmed to ‘0b10’. The WDT is enabled in soft-

ware by setting the SWDTEN control bit (RCON<5>).

The SWDTEN control bit is cleared on any device

Reset. The software WDT option allows the user appli-

cation to enable the WDT for critical code segments

and disables the WDT during non-critical segments for

maximum power savings.

The WDT Time-out flag bit, WDTO (RCON<4>), is not

automatically cleared following a WDT time-out. To

detect subsequent WDT events, the flag must be

cleared in software.

27.6.4

WDT WINDOW

The Watchdog Timer has an optional Windowed mode,

enabled by programming the WINDIS bit in the WDT

Configuration register (FWDT<7>). In the Windowed

mode (WINDIS = 0), the WDT should be cleared based

on the settings in the programmable Watchdog Timer

Window select bits (WDTWIN<1:0>).

FIGURE 27-2:

WDT BLOCK DIAGRAM

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

WDTPRE

WDTPOST<3:0>

Watchdog Timer

Prescaler

(Divide-by-N1)

Postscaler

(Divide-by-N2)

Sleep/Idle

WDT

WDT Window Select

WINDIS

WDT

CLRWDT Instruction

SWDTEN

WDTEN<1:0>

LPRC Clock

Wake-up

Reset

WDTWIN<1:0>

All Device Resets

Transition to New Clock Source

Exit Sleep or Idle Mode

PWRSAV Instruction

CLRWDT Instruction

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