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DSPIC33EP128GS708 Datasheet(PDF) 361 Page - Microchip Technology

Part # DSPIC33EP128GS708
Description  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33EP128GS708 Datasheet(HTML) 361 Page - Microchip Technology

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 2016-2018 Microchip Technology Inc.
DS70005258C-page 361
dsPIC33EPXXXGS70X/80X FAMILY
27.7
JTAG Interface
The dsPIC33EPXXXGS70X/80X family devices imple-
ment a JTAG interface, which supports boundary scan
device testing. Detailed information on this interface is
provided in future revisions of the document.
27.8
In-Circuit Serial Programming™
(ICSP™)
The dsPIC33EPXXXGS70X/80X family devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data, and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to the “dsPIC33E/PIC24E Flash Programming
Specification for Devices with Volatile Configuration
Bits” (DS70663) for details about In-Circuit Serial
Programming™ (ICSP™).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
27.9
In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICE™ emulator is
selected as a debugger, the in-circuit debugging function-
ality is enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging func-
tionality is controlled through the PGECx (Emulation/
Debug Clock) and PGEDx (Emulation/Debug Data) pin
functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
27.10 Code Protection and
CodeGuard™ Security
dsPIC33EPXXXGS70X/80X devices offer multiple levels
of security for protecting individual intellectual property.
The program Flash protection can be broken up into
three segments: Boot Segment (BS), General Segment
(GS) and Configuration Segment (CS). Boot Segment
has the highest security privilege and can be thought to
have limited restrictions when accessing other segments.
General Segment has the least security and is intended
for the end user system code. Configuration Segment
contains only the device user configuration data which is
located at the end of the program memory space.
The code protection features are controlled by the
Configuration registers, FSEC and FBSLIM. The FSEC
register controls the code-protect level for each
segment and if that segment is write-protected. The
size of BS and GS will depend on the BSLIM<12:0> bits
setting and if the Alternate Interrupt Vector Table (AIVT)
is enabled. The BSLIM<12:0> bits define the number of
pages for BS with each page containing 512 IW. The
smallest BS size is one page, which will consist of the
Interrupt Vector Table (IVT) and 256 IW of code
protection.
If the AIVT is enabled, the last page of BS will contain
the AIVT and will not contain any BS code. With AIVT
enabled, the smallest BS size is now two pages
(1024 IW), with one page for the IVT and BS code, and
the other page for the AIVT. Write protection of the BS
does not cover the AIVT. The last page of BS can
always be programmed or erased by BS code. The
General Segment will start at the next page and will
consume the rest of program Flash except for the Flash
Configuration Words. The IVT will assume GS security
only if BS is not enabled. The IVT is protected from
being programmed or page erased when either
security segment has enabled write protection.
Note:
Refer to “Programming and Diagnostics”
(DS70608) in the “dsPIC33/PIC24 Family
Reference Manual” for further information on
usage, configuration and operation of the
JTAG interface.
Note:
Refer to “CodeGuard™ Intermediate
Security” (DS70005182) in the “dsPIC33/
PIC24 Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.



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