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DSPIC33EP128GS708 Datasheet(PDF) 105 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 105 Page - Microchip Technology |
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105 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 105 dsPIC33EPXXXGS70X/80X FAMILY 9.0 OSCILLATOR CONFIGURATION The dsPIC33EPXXXGS70X/80X family oscillator system provides: • On-Chip Phase-Locked Loop (PLL) to Boost Internal Operating Frequency on Select Internal and External Oscillator Sources • On-the-Fly Clock Switching between Various Clock Sources • Doze mode for System Power Savings • Fail-Safe Clock Monitor (FSCM) that Detects Clock Failure and Permits Safe Application Recovery or Shutdown • Configuration Bits for Clock Source Selection • Auxiliary PLL for ADC and PWM A simplified diagram of the oscillator system is shown in Figure 9-1. Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGS70X/80X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Oscillator Module” (DS70005131) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. |
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