ATXP032 datasheet(80/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 13-4. Deep Power-Down in Octal Mode — DDR

13.3

Auto Deep Power-Down Mode after a Program or Erase Operation

The auto deep power-down mode after a program or erase operation allows the device to further reduce its energy

consumption by automatically entering the deep power-down mode after completing an internally timed program or

erase operation. The program or erase operation can be any one of the Block Erase or Chip Erase commands,

Byte/Page Program command or Buffer to Main Memory Page Program without Built-In Erase commands. Note

that the Buffer Write command or any of the Register Write commands do not cause the device to go into deep

power-down mode.

The Auto Deep Power-Down Mode after Program/Erase Operation is enabled by setting the Auto Deep Power-

Down Enable bit in Status/Control Register Byte 2 . The device remains in the same communication mode when

entering and exiting from DPD.

The ADPD bit is cleared every time the device goes into DPD, so it has to be set again if another Program or Erase

operation followed by Auto Deep Power-Down is executed.

13.4

Resume from Deep Power-Down (ABh)

In order to exit the deep power-down mode and resume normal device operation, the Resume from Deep Power-

Down command must be issued. The Resume from Deep Power Down (ABh) command and the Read Status

down mode.

To resume from the deep power-down mode, the CS pin must first be asserted and command of ABh must be

clocked into the device. Any additional data clocked into the device after the command is ignored. When the CS pin

is deasserted, the device exits deep power-down mode within the maximum time of t

RDPD and return to the standby

mode. After issuing the ABh command, the user can check if the device is already out of DPD by checking the

value of DPDS bit in Status/Control register 1.

After the device has returned to the standby mode, normal command operations such as read array can be

resumed.

If the complete command is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on a

whole byte boundary (multiples of eight bits), then the device aborts the operation and return to the deep power-

down mode. The device remains in the same mode (SPI or octal mode) while in deep power-down and wakes up in

the same mode it had before entering deep power-down.

EDPD

ICC

Deep Power Mode Current

Standby Mode Current

Active Current

B9h

Opcode

I/O7-0

SCK

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