ATXP032 datasheet(23/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 8-3.

Read Array — 0Bh Command in Octal Mode SDR

Figure 8-4.

Read Array — 0Bh Command in Octal Mode DDR

8.2

Burst Read with Wrap (0Ch)

In Octal Mode, the “Burst Read with Wrap (0Ch)” instruction is used to perform the read operation with “Wrap

Around” feature.

Microcontroller units (MCU’s) with cache benefit from this feature for eXecute-in-Place (XiP) operations, as it

guarantees an efficient way of reading a whole cache line in one burst regardless of which byte in the cache line

the read starts from. This improves code execution performance in the MCU system, as the MCU first receives the

command or data it requires at that instant, and then the remainder of the cache line, without requiring additional

commands or addresses to be sent.

The continuous mode operation further improves the MCU performance. This mode allows the MCU to directly

load the following cache line if this is required, again without requiring additional commands or addresses to be

sent. This improves the performance of a typical MCU system by 40% or more without increasing system clock

speed.

As an example; The timing for fetching the next consecutive 16-byte cache line on a Flash device with 14 dummy

SPI cycles for eXecute-in-Place (XiP) operations.

In octal SDR mode, the number of cycles will be reduced from 35 to 16:

Command (byte):

1 clock cycle (eliminated for the next consecutive line)

Address (4 bytes):

4 clock cycles (eliminated for the next consecutive line)

Dummy cycles:

14 clock cycles (eliminated for the next consecutive line)

Data (16 Bytes):

16 clock cycles

In octal DDR mode, the number of cycles will be reduced from 25 to 8:

Command (byte):

0.5 clock cycles (eliminated for the next consecutive line)

Byte1

Byte2

Output Data

Dummy Cycles

A23-16

A15-8

A7-0

A31-24

Address

0Bh

Opcode

n+1

I/O7-0

SCK

Output

Data

Byte1 Byte2

Dummy Cycles

Address

Bits A

-A

0Bh

Opcode

I/O7-0

SCK

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