ATXP032 datasheet(11/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Memory Architecture

To provide the greatest flexibility, the memory array of the ATXP032 is divided into three levels of granularity

comprised of sectors, blocks, and pages. The size of the erase blocks is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own erase regions. Figure 5-1, Memory

Architecture Diagram, illustrates the breakdown of each level and details the number of pages per sector and

block. Program operations to the memory array can be done at the full page level or at the byte level (a variable

number of bytes). The erase operations can be performed at the chip level or at 3 different block size levels.

CC,VCC I/O

DEVICE POWER SUPPLY: The VCC and VCC I/O pins are used to supply the source voltage to

the device. The V

CC and VCC I/O pins have to be connected to the same supply voltage.

Each V

CC and VCC I/O pin requires a separate decoupling capacitor to GND. 1 µF ceramic

capacitors are recommended.

Operations at invalid V

CC voltages may produce spurious results and should not be attempted.

Power

GND,

GND I/O

GROUND: The ground reference for the power supply. GND and GND I/O should be

connected to the system ground.

Power

RESET

RESET: A low state on the reset pin (RESET) terminates the operation in progress and resets

the internal state machine to an idle state. The device remains in the reset condition as long as

a low level is present on the RESET pin. Normal operation can resume once the RESET pin is

brought back to a high level. See

Section 13.10 for details about the device operation when

RESET pin is engaged. The device incorporates an internal power-on reset circuit, so there

are no restrictions on the RESET pin during power-on sequences.

If this pin and feature is not utilized, then it is recommended that the RESET pin is driven high

externally. It has an internal pull-up, and may alternatively be left open.

The RESET pin is not required for operation of the device. The

JEDEC Standard Hardware

Reset (In-Band Reset) function described in Section 13.9 provides the same functions

without requiring a dedicated pin. The RESET pin is included for compatibility with older

systems. For new designs, the

JEDEC Standard Hardware Reset (In-Band Reset) is

recommended.

The RESET pin may not be included in all package options.

Low

Input

Table 4-1.

Pin Descriptions (Continued)

Symbol

Description

Asserted

State

Type

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