DLPA2005 datasheet(31/60 Pages) TI

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7.3.4.2 SPI Flash Programming

The SPI pins of the flash can directly be driven for flash programming while the DLPC1438 controller I/Os are

tri-stated. SPI0_CLK, SPI0_DOUT, and SPI0_CSZ0 I/O can be tri-stated by holding RESETZ in a logic low state

while power is applied to the controller. The logic state of the SPI0_CSZ1 pin is not affected by this action.

Alternatively, the DLPC1438 controller can program the SPI flash itself when commanded via I2C if a valid

firmware image has already been loaded and the controller is operational.

7.3.5 I2C Interface

Both of the DLPC1438 I2C interface ports support a 100-kHz baud rate. Because I2C interface transactions

operate at the speed of the slowest device on the bus, there is no requirement to match the speed of all devices

in the system.

7.3.6 Test Point Support

The DLPC1438 test point output port, TSTPT_(7:0), provides selected system calibration and controller debug

support. These test points are inputs when reset is applied. These test points are outputs when reset is released.

The controller samples the signal state upon the release of system reset and then uses the captured value

to configure the test mode until the next time reset is applied. Because each test point includes an internal

pulldown resistor, external pullups must be used to modify the default test configuration.

The default configuration (b000) corresponds to the TSTPT_(2:0) outputs remaining tri-stated to reduce

switching activity during normal operation. For maximum flexibility, a jumper to external pullup resistors is

recommended for TSTPT_(2:0). The pullup resistors on TSTPT_(2:0) can be used to configure the controller

for a specific mode or option. TI does not recommend adding pullup resistors to TSTPT_(7:3) due to potentially

adverse effects on normal operation. For normal use TSTPT_(7:3) should be left unconnected. The test points

are sampled only during a 0-to-1 transition on the RESETZ input, so changing the configuration after reset is

released does not have any effect until the next time reset asserts and releases. Table 7-8 describes the test

mode selections for one programmable scenario defined by TSTPT_(2:0).

Table 7-8. Test Mode Selection Scenario Defined by TSTPT_(2:0)

TSTPT OUTPUT VALUE(1)

NO SWITCHING ACTIVITY

CLOCK DEBUG OUTPUT

TSTPT_(2:0) = 0b000

TSTPT_(2:0) = 0b010

TSTPT_0

HI-Z

60 MHz

TSTPT_1

HI-Z

30 MHz

TSTPT_2

HI-Z

0.7 to 22.5 MHz

TSTPT_3

HI-Z

HIGH

TSTPT_4

HI-Z

LOW

TSTPT_5

HI-Z

HIGH

TSTPT_6

HI-Z

HIGH

TSTPT_7

HI-Z

7.5 MHz

(1)

These are default output selections. Software can reprogram the selection at any time.

7.3.7 DMD Interface

The DLPC1438 controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface

and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.

7.3.7.1 Sub-LVDS (HS) Interface

The DLP300S/DLP301S DMD does not require all of the available output data lanes of the controller. Internal

software selection allows the controller to support multiple DMD interface swap configurations. These options

can improve board layout by remapping specific combinations of DMD interface lines to other DMD interface

lines as needed. Table 7-9 shows the two options available for the DLP300S/DLP301S DMD. Leave any unused

DMD signal pairs unconnected on the final board design.

www.ti.com

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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