DLPA2005 datasheet(6/60 Pages) TI

6 / 60 page

Table 5-3. DSI Input Data and Clock

I/O

Type(1)

DESCRIPTION

NAME

NO.

DCLKN

DCLKP

---

unused; Leave unconnected and floating.

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

---

unused; Leave unconnected and floating.

RREF

—

---

Leave this pin unconnected and floating.

(1)

See Table 5-10 for type definitions.

Table 5-4. DMD Reset and Bias Control

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

DMD_DEN_ARSTZ

DMD driver enable (active high). DMD reset (active low). When

corresponding I/O power is supplied, the controller drives this signal low

after the DMD is parked and before power is removed from the DMD. If

the 1.8-V power to the DLPC1438 is independent of the 1.8-V power to the

DMD, then TI recommends including a weak, external pulldown resistor to

hold the signal low in case DLPC1438 power is inactive while DMD power

is applied.

DMD_LS_CLK

DMD, low speed (LS) interface clock

DMD_LS_WDATA

DMD, low speed (LS) serial write data

DMD_LS_RDATA

DMD, low speed (LS) serial read data

(1)

See Table 5-10 for type definitions.

Table 5-5. DMD Sub-LVDS Interface

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

DMD_HS_CLK_P

DMD_HS_CLK_N

DMD high speed (HS) interface clock

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A10

B10

A11

B11

DMD sub-LVDS high speed (HS) interface write data lanes. The true

numbering and application of the DMD_HS_WDATA pins depend on the

software configuration. See Table 7-9.

(1)

See Table 5-10 for type definitions.

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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