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DLPA2005 Datasheet(PDF) 45 Page - Texas Instruments |
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DLPA2005 Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 60 page ![]() VSS VDD VSS_ PLLD VDD_ PLLD VSS VSS_ PLLM Signal VSS F J H A 3 2 VDD PLL_ REF CLK_I Signal 4 VDD_ PLLM 1 Signal VSS 5 Controller pad PCB pad Local decoupling for the PLL digital supply FB Signal Signal PLL_ REF CLK_O FB Crystal Circuit 1.1-V Power GND G signal via via to common analog digital board power plane via to common analog digital board ground plane Figure 10-1. PLL Filter Layout 10.1.2 Reference Clock Layout The DLPC1438 controller requires an external reference clock to feed the internal PLL. Use either a crystal or oscillator to supply this reference. The DLPC1438 reference clock must not exceed a frequency variation of ±200 ppm (including aging, temperature, and trim component variation). www.ti.com DLPC1438 DLPS216A – JULY 2021 – REVISED AUGUST 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: DLPC1438 |
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