DLPA2005 datasheet(26/60 Pages) TI

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7.3 Feature Description

7.3.1 Input Source

7.3.1.1 Supported Resolution and Frame Rates

Table 7-1. Supported Input Source Ranges(1) (2) (3)

INTERFACE

Bits / Pixel (4)

SOURCE RESOLUTION RANGE(5)

FRAME RATE

RANGE

HORIZONTAL

VERTICAL

Landscape

Portrait

Landscape

Portrait

Parallel

1280

720

1280

60 ±2 Hz

(1)

The application must remain within specifications for all source interface parameters such as maximum clock rate and maximum line

rate.

(2)

The maximum DMD size for all rows in the table is 1280 × 720.

(3)

To achieve the ranges stated, the firmware must support the source parameters. Review the firmware release notes or contact TI to

determine the latest available frame rate and input resolution support for a given firmware image.

(4)

Bits per pixel does not necessarily equal the number of data pins used on the DLPC1438 controller.

(5)

By using an I2C command, portrait image inputs can be rotated on the DMD by minus 90 degrees so that the image is displayed in

landscape format.

7.3.1.2 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes the signals listed in

Table 7-2.

Table 7-2. Parallel Interface Signals

SIGNAL

DESCRIPTION

VSYNC_WE

vertical sync

HSYNC_CS

horizontal sync

DATAEN_CMD

data valid

PDATA

8-bit data bus

PCLK

pixel clock

PDM_CVS_TE

parallel data mask (optional)

Note

VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no

longer active, the display sequencer stops and causes the LEDs to turn off.

The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section

shows the relationship of these signals.

An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without

losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source

image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or

active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic

low signal. PDM_CVS_TE must only change during vertical blanking.

The parallel interface supports a single 8-bit data format with bitweights as defined in Table 5-2.

7.3.2 External Print

External Print is one of the key capabilities of the DLPC1438 controller. When the DLPC1438 controller is

configured for external print, most video processing functions are bypassed to allow for accurate pattern display.

In external print mode, frame data is sent to the DLPC1438 controller over parallel interface. Commands to the

DLPC1438 controller execute a printed layer with a programmable number of frames to expose before disabling

illumination to prepare for the next print layer.

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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