DLPA2005 datasheet(37/60 Pages) TI

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8.2.2 Pattern projector for 3D printer with actuator

DLPC1438 controller with DLP300S/DLP301S DMD enables high accuracy and low cost 3D printer products.

Figure 8-3 shows a typical 3D printer system block diagram using external print mode.

Illumination

optics

DLPC1438

DMD

DLPA200x

TI DLP Chipset

Non-TI Device

VBIAS, VOFFSET,

VRESET

SYSPWR

Sub-LVDS DATA

PROJ_ON

HOST_IRQ

Flash

SPI (4)

VLED

CTRL

RLIM

1.8 V external

1.8 V

PROJ_ON

VCC_18

VCC_INTF

VCC_FLSH

VDD

SPI (4)

INTZ

Thermistor

VDDLP12

SPI0

SPI1

RESETZ

PARKZ

GPIO_8

GPIO_10

CMP_OUT

1.8 V

1.1 V

Front End

Processor

Supplies

VSPI

1.8 V

1.1 Reg

1.1 V

LED_SEL (2)

RC_

CHARGE

1.8 V

FPGA

Parallel (12)

SPI_RDY

FPGA_READY

Flash

Frame

Memory

Actuator

Driver

Actuator

ACT_SYNC

Figure 8-3. Internal Pattern Streaming Mode

8.2.2.1 Design Requirements

When higher resolution is required, a front-end FPGA design is provided which provides actuator control and

synchronization, as well as providing a data bridge between an SPI output of a host processor and the parallel

interface of the DLPC1438. This FPGA combined with the DLP300S/DLP301S, DLPC1438, and DLPA200x

PMIC/LED driver complete the control electronics for the optical module of a 3D printer. In addition to the DLP

chipset, other IC components may be needed including a flash device to store the software and firmware to

control the DLPC1438.

A 405nm LED typically supplies the illumination for the DMD. In addition to LEDs, other light sources are

supported.

For connecting the DLPC1438 controller to the host processing for receiving patterns or video data, the parallel

interface is used. Connect an I2C interface to the host processor to send commands to the DLPC1438 controller.

8.2.2.2 Detailed Design Procedure

For connecting the DLP300S/DLP301S DMD, the DLPC1438 controller and the DLPA200x or DLPA300x

PMIC/LED driver see the reference design schematic. Follow the layout guidelines shown in Section 10 to

achieve reliable DLP system results.

8.2.2.3 Application Curve

See the Section 8.2.1.3 as the brightness considerations are similar in systems with and without an FPGA.

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DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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