DLPA2005 datasheet(39/60 Pages) TI

39 / 60 page

Chipset State

PROJ_ON

SYSPWR

FPGA_RDY

VCC18 (1.8V)

VDD (1.1V)

RESETZ

HOST_IRQ

I2C

PARKZ

PLL_REFC

FPGA PWR

Signals

from PMIC (DLPA3000)

PWR Off

VIN On

PWR On

Pre-Initialization

Initialization

Regular operation

(a)

(b)

(c)

(d)

from other source

VCC_INTF (1.8V)

VCC_FLSH (1.8V)

t1:

SYSPWR (VIN) applied to the PMIC. All other voltage rails are derived from SYSPWR.

t2:

All DLPC1438 supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a

different external supply.

t3:

Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.

t4:

HOST_IRQ goes low to indicate initialization is complete. I2C is now ready to accept commands.

(a):

The typical delay between the PLL reference clock becoming active and RESETZ being deasserted (going high) is less than 1

ms. PLL_REFCLK must be stable within 5 ms of all power being applied, and may be active before power is applied.

(b):

There is a typical controller boot time of 100 ms. PARKZ must be high before RESETZ releases to support auto-initialization.

RESETZ must also be held low for at least 5 ms after DLPC1438 power supplies are in specification.

(c):

There is a typical FPGA setup time of 2.75 ms before the system completes boot process. During this period, the DLPC1438

controller writes startup values to the FPGA registers.

(d):

After FPGA setup is complete, I2C now accepts commands.

Figure 9-1. DLPC1438 Power-Up Timing

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DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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DLPA2005 Datasheet(PDF) 39 Page - Texas Instruments

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