DLPA2005 datasheet(40/60 Pages) TI

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System State

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDDLP12

(if not tied to VDD)

VDD_PLLM/D (1.1 V)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

RESETZ

HOST_IRQ

2C (activity)

(b)

(c)

Regular operation

Normal

Park

Power supply shutdown

Signals

from PMIC (DLPA3000)

from other source

(a)

FPGA PWR

t1:

PROJ_ON goes low to begin the power down sequence.

t2:

The controller finishes parking the DMD.

t3:

Controller power supplies are turned off.

(a):

The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and

VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON

is deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore

recommended to follow note (c).

(b):

DMD reset voltage regulation stops typically after 12 ms of normal DMD park being completed.

(c):

It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the

DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.

Figure 9-2. DLPC1438 Normal Power-Down

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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DLPA2005 Datasheet(PDF) 40 Page - Texas Instruments

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