DLPA2005 datasheet(9/60 Pages) TI

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Table 5-7. GPIO Peripheral Interface(1) (continued)

PIN(1)

I/O

TYPE(3)

DESCRIPTION(2)

NAME

NO.

GPIO_04

E14

I/O

General purpose I/O 04 (hysteresis buffer). Options:

SPI1_CSZ1 (active-low output): Optional SPI1 chip select 1 signal. Requires an external pullup

resistor to deactivate this signal during reset and auto-initialization processes.

Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and

left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating

GPIO input.

GPIO_03

D15

I/O

General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal.

This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to

deactivate this signal during reset and auto-initialization processes.

GPIO_02

D14

I/O

General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is

typicallyconnected to the DLPAxxxx SPI_DIN pin.

GPIO_01

C15

I/O

General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically

connected to the DLPAxxxx SPI_CLK pin.

GPIO_00

C14

I/O

General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is

typically connected to the DLPAxxxx SPI_DOUT pin.

(1)

GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or

more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as

open-drain.

(2)

General purpose I/O for the DLPC1438 controller. These GPIO pins are software configurable.

(3)

See Table 5-10 for type definitions.

Table 5-8. Clock and PLL Support

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

PLL_REFCLK_I

Reference clock crystal input. If an external oscillator is used instead of a crystal, use

this pin as the oscillator input.

PLL_REFCLK_O

Reference clock crystal return. If an external oscillator is used instead of a crystal,

leave this pin unconnected (floating with no added capacitive load).

(1)

See Table 5-10 for type definitions.

Table 5-9. Power and Ground

I/O

TYPE

DESCRIPTION

NAME

NO.

VDD

C5, D5, D7,

D12, J4,

J12, K3, L4,

L12, M6,

M9, D9,

D13, F13,

H13, L13,

M10, D3, E3

—

PWR

Core 1.1-V power (main 1.1 V)

VDDLP12

—

---

Unused. It is recommended to externally tie this pin to VDD.

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DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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