DLPA2005 datasheet(38/60 Pages) TI

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9 Power Supply Recommendations

9.1 PLL Design Considerations

It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.

However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC1438 requires an array of power supply voltages, (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, VCC_INTF), because VDDLP12 is tied to the 1.1-V VDD supply, then there

are no restrictions regarding the relative order of power supply sequencing to avoid damaging the controller

(This is true for both power-up and power-down scenarios). Similarly, there is no minimum time between

powering-up or powering-down the different supplies if VDDLP12 is tied to the 1.1-V VDD supply.

Although there is no risk of damaging the controller if the above power sequencing rules are followed, the

following additional power sequencing recommendations must be considered to ensure proper system operation.

• To ensure that DLPC1438 output signal states behave as expected, all controller I/O supplies should remain

applied while VDD core power is applied. If VDD core power is removed while the I/O supply (VCC_INTF) is

applied, then the output signal state associated with the inactive I/O supply goes to a high impedance state.

• Additional power sequencing rules may exist for devices that share the supplies with the controller, and thus

these devices may force additional system power sequencing requirements.

Note that when VDD core power is applied, but I/O power is not applied, additional leakage current may be

drawn. This added leakage does not affect normal controller operation or reliability.

Figure 9-1, Figure 9-2 and Figure 9-3 show the controller power-up and power-down sequence for both the

normal PARK and fast PARK operations of the DLPC1438 controller.

Note

During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms

after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely

power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended

that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least

50 ms after PROJ_ON goes low.

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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DLPA2005 Datasheet(PDF) 38 Page - Texas Instruments