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6.15 Flash Interface Timing Requirements

The DLPC3478 flash memory interface consists of a SPI flash serial interface. The DLPC3478 can support 1- to 128-Mb

flash memories.(2) (3) (4)

MIN

MAX

UNIT

fclock

SPI_CLK frequency

See (1)

1.4

36.0

MHz

tp_clkper

SPI_CLK period

50% reference points

27.8

704

tp_wh

SPI_CLK pulse duration high

50% reference points

352

tp_wl

SPI_CLK pulse duration low

50% reference points

352

Transition time – all signals

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

0.2

3.0

tp_su

Setup time – SPI_DIN valid before SPI_CLK falling edge 50% reference points

10.0

tp_h

Hold time – SPI_DIN valid after SPI_CLK falling edge

50% reference points

0.0

tp_clqv

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

50% reference points

1.0

tp_clqx

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

50% reference points

–3.0

3.0

(1)

This range include the ±200 ppm of the external oscillator (but no jitter).

(2)

Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3478 does

transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI

devices with long clock-to-Q timing. DLPC3478 hold capture timing has been set to facilitate reliable operation with standard external

SPI protocol devices.

(3)

With the above output timing, DLPC3478 provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the

rising edge of SPI_CLK.

(4)

For additional requirements of the external flash device view the Section 7.3.4 section.

SPI_CLK

(Controller output)

SPI_DIN

(Controller input)

SPI_DOUT, SPI_CS(1:0)

(Controller output)

tCLKPER

tWH

tWL

tP_CLQV

tP_CLQX

tP_SU

tP_H

Figure 6-10. Flash Interface Timing

6.16 Other Timing Requirements

MIN

MAX

UNIT

trise, all(1) (2)

20% to 80% reference points

tfall, all(1) (2)

80% to 20% reference points

trise, PARKZ(2)

20% to 80% reference points

150

tfall, PARKZ(2)

80% to 20% reference points

150

tw, GPIO_08 (normal park) pulse width(3)

200

I2C baud rate

100

kHz

(1)

Unless noted elsewhere, the following signal transition times are for all DLPC34xx signals.

(2)

This is the recommended signal transition time to avoid input buffer oscillations.

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DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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