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6.14 BT656 Interface General Timing Requirements

The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate

ITU-R BT.656 specification for detailed interface timing requirements. (2)

MIN

MAX

UNIT

ƒcll

PCLK frequency

1.0

33.5

MHz

tp_clkper

PCLK period

50% reference points

29.85

1000

tp_clkjit

PCLK jitter

Max fclock

See (1)

tp_wh

PCLK pulse duration high

50% reference points

10.0

tp_wl

PCLK pulse duration low

50% reference points

10.0

tp_su

Setup time – PDATA(7:0) before the active edge of

PCLK

50% reference points

3.0

tp_h

Hold time – PDATA(7:0) after the active edge of

PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference points

(rising signal)

80% to 20% reference points

(falling signal)

0.2

3.0

(1)

Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Clock jitter must maintain setup and hold times. BT.656 data

bits must be mapped to the DLPC34xx PDATA bus as shown in Figure 6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA (23:0)

mapping.

(2)

The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK. See Figure 6-9.

Bus assignment mapping

PDATA(7:0) of the input pixel data bus

Data bit mapping on controller pin

n/a

Figure 6-9. BT.656 Interface Mode Bit Mapping

DLPC1438

DLPS216A – JULY 2021 – REVISED AUGUST 2021

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