LTC3889 datasheet(71/118 Pages) AD

71 / 118 page

LTC3888/LTC3888-1/

LTC3888-2

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

PMBus communication rate, the resistor pull-up on the

SDA and SCL pins with the time constant set to one-third

the required rise time equals

RPULLUP =

tRISE

3 • 100pF

= 1k

The closest 1% resistor value is 1kΩ. Limit to 1.1kΩ for

best noise margin.

Be careful to minimize parasitic capacitance on the SDA

and SCL lines to avoid communication problems. To esti-

mate the loading capacitance, monitor the signal in ques-

tion and measure how long it takes for the desired signal

to reach approximately 63% of the output value. This is

one time constant.

The SYNC pin has an on-chip pull-down transistor with

the output held low for nominally 500ns when driven by

the LTC3888. If the internal oscillator is set for 500kHz

and the load is 100pF with a one-third rise time required,

the resistor calculation is as follows:

RPULLUP =

2µs – 500ns

3 • 100pF

= 5.0k

The closest 1% resistor is 4.99kΩ .

If timing errors are occurring or if the SYNC amplitude is not

as large as required, monitor the waveform and determine

if the RC time constant is too long for the application. If

possible reduce the parasitic capacitance. Otherwise reduce

the pull-up resistor sufficiently to assure proper operation.

Similar results (R < 5kΩ) should be applied to the

PGOOD0 output when configured as CLKOUT to ensure

proper clocking of the slave IC.

The SHARE_CLK output has a nominal period of 10μs

and is pulled low for about 1μs. If the system load on this

shared line is 100pF, the resistor calculation for this line

with a one-third rise time is:

RPULLUP =

9µs

3 • 100pF

= 30k

The closest 1% resistor is 30.1kΩ .

PMBUS COMMUNICATION AND COMMAND

PROCESSING

The LTC3888 has a one deep buffer to hold the last data

written for each supported command prior to processing,

as shown in Figure 45. Two distinct parallel sections of the

LTC3888 manage command buffering and command pro-

cessing to ensure the last data written to any command is

never lost. When the part receives a new command from

the bus, command data buffering copies the data into the

write command data buffer and indicates to the internal

processor that data for that command should be handled.

The internal processor runs in parallel and performs the

sometimes slower task of fetching, converting (to internal

format) and executing commands marked for processing.

Some computationally intensive commands (e.g., timing

parameters, temperatures, voltages and currents) have

internal processor execution times that may be long rela-

tive to PMBus timing. If the part is busy processing a

command, and a new command(s) arrives, execution may

be delayed or processed in a different order than received.

The part indicates when internal calculations are in pro-

cess with bit 5 of MFR_COMMON (Internal Calculations

Not Pending). When the internal processor is busy cal-

culating, bit 5 is cleared. When this bit is set, the part is

ready for another command. An example polling loop is

provided in Figure 46, which ensures that commands are

processed in order while simplifying error handling rou-

tines. MFR_COMMON always returns valid data at PMBus

speeds between 10kHz and 400kHz.

Figure 45. Write Command Data Processing

DECODER

CMD

INTERNAL

PROCESSOR

WRITE COMMAND

DATA BUFFER

PAGE

CMDS

0x00

0x21

0xFD

388812 F45

•

MFR_RESET

VOUT_COMMAND

CALCULATIONS

PENDING

PMBus

WRITE

FETCH,

CONVERT

DATA

AND

EXECUTE

DATA

MUX

LTC3889 Datasheet(PDF) 71 Page - Analog Devices

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