LTC3889 datasheet(29/118 Pages) AD

29 / 118 page

LTC3888/LTC3888-1/

LTC3888-2

Rev. B

For more information www.analog.com

OPERATION

The VOUT0_CFG and VOUT1_CFG (LTC3888/3888-2) or

the ILIM0_CFG and ILIM1_CFG (LTC3888-1) pin settings

are described in application Table 10. These pins select

the per-phase output voltage (LTC3888/3888-2) or cur-

rent limit (LTC3888-1) for each related rail.

For more details on the LTC3888-1 voltage settings refer

to the Classical Analog Output Voltage Control section.

For the LTC3888 the VOUTn_CONFIG pins set the desired

output voltage. In addition, the following parameters are

set as a percentage of the programmed VOUT.

• VOUT_OV_FAULT_LIMIT: +10%

• VOUT_OV_WARN+LIMIT: +7.5%

• VOUT_MARGIN_HIGH: 5%

• VOUT_MARGIN_LOW: -5%

• VOUT_UV_WARN_LIMIT: -6.5%

• VOUT_UV_FAULT_LIMIT: -7.5%

PWM_CFG pin settings are described in application

Table 11. This pin selects the master/slave configurnation

and switching frequency of the internal oscillator.

INTERNAL EEPROM WITH CRC

The LTC3888 contains internal EEPROM with error cor-

rection code (ECC) to store user configuration settings

and fault log information. EEPROM endurance and reten-

tion for user space and fault log pages are specified in the

Absolute Maximum Ratings and Electrical Characteristics

table.

The integrity of the entire onboard EEPROM is checked

with a CRC calculation each time its data is to be

read, such as after a power-on reset or execution of

RESTORE_USER_ALL. If a CRC error occurs, the CML

bit is set in STATUS_BYTE and STATUS_WORD, the

EEPROM CRC Error bit in STATUS_MFR_SPECIFIC is set,

and the ALERT, SHARE_CLK and RUN pins are pulled low

(PWM channels off). At that point the device will respond

at special address 0x7C, which is activated after an invalid

CRC has been detected. The chip no longer responds at

its specifically assigned address, but will still respond at

global addresses 0x5A and 0x5B. However, use of these

global addresses when attempting to recover from a CRC

issue is not recommended. All power supply rails associ-

ated with a device reporting an invalid CRC should remain

disabled until the issue is resolved.

ADI recommends that the EEPROM not be written when

die temperature is greater than 85°C. If internal die tem-

perature exceeds 130°C, all EEPROM operations except

RESTORE_USER_ALL and MFR_RESET are disabled. Full

EEPROM operation is not re-enabled until die temperature

falls below 125°C. Refer to the Applications Information

section for equations to predict retention degradation due

to elevated operating temperatures.

See the Applications Information section or contact the

factory for details on efficient in-system EEPROM pro-

gramming, including bulk EEPROM programming, which

the LTC3888 also supports.

FAULT DETECTION

A variety of fault and warning detection, reporting and

handling mechanisms are provided by the LTC3888. Fault

or warning detection capabilities include:

• Input Under/Overvoltage

• Power Stage UV or Fault

• Output Under/Overvoltage

• Output Overcurrent

• External Overtemperature

• Internal Overtemperature

• CML Fault (Communication, Memory, or Logic)

• External Fault Detection via Bidirectional FAULT Pins

LTC3889 Datasheet(PDF) 29 Page - Analog Devices

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