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LTC3889 Datasheet(PDF) 16 Page - Analog Devices |
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LTC3889 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 118 page ![]() LTC3888/LTC3888-1/ LTC3888-2 16 Rev. B For more information www.analog.com PIN FUNCTIONS RUN0/RUN1(Pin20/Pin21):RunControlInputsandOpen- Drain Outputs. A voltage above 1.5V (LTC3888/3888-2) and 2V (LTC3888-1) is required on these pins to enable the respective PWM master channel. The LTC3888/3888-1/ 3888-2 may drive these pins low under certain reset/ restart conditions regardless of any PMBus command settings. A pullup resistor is required in the application. RSET (Pin 22): Resistor Configuration Set Input. Connect a 1% 18.7kΩ resistor between this pin and GND to set the selection values for the configuration resistors for programming bus address, output current limit and other PWM settings. Refer to the Applications Information sec- tion for more details. ASEL0/ASEL1 (Pin 23, Pin 24): PMBus Serial Address Select Inputs. Connect optional 1% resistors between these pins and GND to select the serial bus interface address. Refer to the Applications Information section for more detail. VOUT0_CFG/VOUT1_CFG (LTC3888/3888-2), ILIM0_ CFG/ILIM1_CFG (LTC3888-1) (Pin 25/Pin 26): Output Voltage (LTC3888/3888-2), Output Current Limit (LTC3888-1) Configuration Inputs. Connect optional 1% resistors between these pins and GND to select the output current limit for each channel. Refer to the Applications Information section for more detail. PWM_CFG (Pin 27): PWM Configuration Input. Connect an optional 1% resistor between this pin and GND to con- figure PWM switching frequency and master/slave con- figuration. Refer to the Applications Information section for more detail. VDD25 (Pin 28): Internal 2.5V Regulator Output. Bypass this pin to GND with a low ESR 1μF capacitor. Do not load this pin with external current. SDI (LTC3888 Pin 12): Serial Data Input. This pin pro- vides input data for the Serial Peripheral Interface (SPI). Ground this pin if not used. SCK (LTC3888 Pin 13): Serial Clock Input. This pin pro- vides the input data clock for the SPI. Ground this pin if not used. SERR (LTC3888 Pin 34): Open-Drain SPI Status Output. This pin is pulled low if a SPI transmission error is detected. Do not wire this pin to a standard (shared) SPI SDO line. Refer to the Operation section for more detail. A pull-up resistor is required in the application. This pin should be left open if not used. SCS (LTC3888 Pin 35): SPI Chip Select Input. This active- low input is used to enable the LTC3888 to receive a SPI data transmission. Wire this pin to VDD33 if not used. SHARE_CLK (Pin 29): Share Clock Input and Open- Drain Output. Share clock, nominally 100kHz, is used to sequence multiple rails in a power system utilizing more than one ADI PMBus controller. A pull-up resistor to 3.3V is required in the application. Minimize the capacitance on this line to ensure the time constant is fast enough for the application. VDD33 (Pin 30): Internal 3.3V Regulator Output. Bypass this pin to GND with a low ESR capacitor (1µF to 2.2µF). The LTC3888/3888-1/3888-2 may also be powered from an external 3.3V source attached to this pin for program- ming purposes only, if the device is otherwise unpow- ered. Connect only external passive components for LTC3888/3888-1/3888-2 configuration and application. INTVCC (Pin 31): 5.2V Regulator Output. Bypass this pin to GND with a low ESR 4.7μF capacitor. Connect only external passive components for LTC3888/3888-1/3888-2 configuration and application. VIN (Pin 32): Main Input Supply. Decouple this pin to GND with a low ESR capacitor (0.1µF to 2.2µF). In applications where VIN will always operate below 6V, short this pin and INTVCC together. IREF (Pin 33): DrMOS Current Sense Reference. This voltage output provides reference bias for floating current monitors from DrMOS devices. Decouple this pin to GND (exposed pad) at the LTC3888/3888-1/3888-2 and each power stage with 100nF to 1μF using low ESR capacitors. GND (Exposed Pad Pin 53): Ground. All small-signal and compensation components should connect to this pad. The exposed pad must be soldered to a suitable PCB cop- per ground plane for proper electrical operation and to obtain the specified package thermal resistance. |
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