CS48L32 datasheet(43/192 Pages) CIRRUS

43 / 192 page

DS1219F4

Cirrus Logic

CS48L32

4.3 Digital Core

The CS48L32 digital core provides extensive mixing and processing capabilities for multiple signal paths. The

configuration is highly flexible and supports virtually every conceivable input/output connection between the available

processing blocks.

The digital core provides parametric equalization (EQ) functions, DRC, and low-/high-pass filters (LHPF).

The CS48L32 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided

to allow digital audio to be routed between input (ADC/PDM) paths and audio serial ports (ASP1–ASP2) operating at

different sample rates.

The DSP functions are programmable, using application-specific control sequences. Note that the DSP configuration data

is lost whenever the VDD_D power domain is removed; the DSP configuration data must be downloaded to the CS48L32

each time the device is powered up.

The CS48L32 incorporates a tone generator that can be used for beep functions through any of the audio signal paths. A

white-noise generator is incorporated, to provide comfort noise in cases where silence (digital mute) is not desirable.

Two pulse-width modulation (PWM) signal generators are provided; the PWM waveforms can be modulated by an audio

source within the digital core and can be output on a GPIO pin.

An overview of the digital-core mixing and signal-processing functions is provided in Fig. 4-15. The control registers

associated with the digital-core signal paths are shown in Fig. 4-16 through Fig. 4-27. The full list of digital mixer control

registers (0x8080–0x907C) is provided in Section 6. Generic register field definitions are provided in Table 4-10.

The digital audio core is predominantly a 24-bit architecture, but also provides support for 32-bit signal paths. Audio

samples of up to 32 bits are supported by the ASP functions. The respective signal mixers provide full support for 32-bit

data words. Note that all other signal paths and signal-processing blocks within the digital core are limited to 24-bit data

length; data samples are truncated to 24-bit length if they are routed through any function that does not support 32-bit data

words.

CS48L32 Datasheet(PDF) 43 Page - Cirrus Logic