CS48L32 datasheet(79/192 Pages) CIRRUS

79 / 192 page

DS1219F4

Cirrus Logic

CS48L32

4.5 DSP Peripheral Control

4.4.4

DSP Interrupts

The Halo Core DSP incorporates a comprehensive interrupt controller, supporting a flexible capability to take input from

many different events and status indications, and to adapt the program flow according to different priority levels assigned

to each event. A high-priority non-maskable interrupt (NMI) is provided in case of a serious failure mode requiring a reset

of the DSP.

The DSP also provides input to the device-level interrupt controller. The DSP-derived inputs to the CS48L32 interrupt

controller include DSP error indications and general-purpose interrupt signals under control of the DSP firmware.

The following events are supported as inputs to the CS48L32 interrupt controller:

• Memory protection error

• Watchdog timeout

• Memory controller error

• AHB system error

• AHB packing error

• NMI error

• General-purpose IRQ 0–3

• Trace buffer stack error

• MIPS profile 1 done

• MIPS profile 0 done

See Section 4.9 for further details of the CS48L32 interrupt controller.

4.5 DSP Peripheral Control

The CS48L32 incorporates a suite of DSP peripheral functions that can be integrated together to provide an enhanced

capability for DSP applications. Configurable event log functions provide multichannel monitoring of internal and external

signals. The general-purpose timers provide time-stamp data for the event logger; they also provide input to the

alarm-generator circuits, enabling time-dependent interrupt events to be generated. Maskable GPIO provides an efficient

mechanism for the Halo Core DSP to access the required input and output signals. The quad-SPI (QSPI) master interface

enables high-speed data transfers between the DSP and external components such as flash-memory devices.

The DSP peripherals are designed to provide a comprehensive DSP capability, operating with a high degree of autonomy

from the host processor.

4.5.1

Event Logger

The CS48L32 provides an event-log function, supporting multichannel, edge-sensitive monitoring and recording of internal

or external signals.

4.5.1.1

Overview

The event logger allows status information to be captured from a large number of sources, to be prioritized and acted upon

as required. For the purposes of the event logger, an event is recorded when a logic transition (edge) is detected on a

selected signal source.

The logged events are held in a FIFO buffer, which is managed by the application software. A 32-bit time stamp, derived

from one of the general-purpose timers, is associated and recorded with each FIFO index, to provide a comprehensive

record of the detected events.

The event logger is associated with one of the general-purpose timers (see Section 4.5.3). The selected timer is the source

of time stamp data for any logged events.

CS48L32 Datasheet(PDF) 79 Page - Cirrus Logic

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