CS48L32 datasheet(14/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-14. AUX PDM Interface Timing

The following timing information is valid across the full range of recommended operating conditions.

Parameter 1

1.AUX PDM interface timing.

Symbol

Minimum

Typical

Maximum

Units

Master Mode

AUXPDMn_CLK cycle time

tCY

320

—

1432

AUXPDMn_CLK duty cycle

—

AUXPDMn_CLK rise/fall time (25 pF load, VDD_IO = 1.8 V)

tr, tf

—

AUXPDMn_DOUT valid from active CLK edge

Analog input

tDV

—

AUXPDMn_DOUT hold from active CLK edge

Analog input

tHO

0—

—

AUXPDMn_DOUT propagation delay 2

2.DOUT propagation delay is measured from a rising/falling edge on INn_PDMDATA to the corresponding edge at AUXPDMn_DOUT.

Digital input

tDD

—

AUXPDMn_CLK phase alignment 3

3.In Master Mode, CLK phase alignment represents the timing of the AUXPDMn_CLK signal with respect to the INn_PDMCLK.

Digital input

tCD

–5

—

Slave Mode

AUXPDMn_CLK cycle time

tCY

320

—

1432

AUXPDMn_CLK duty cycle

—

AUXPDMn_DOUT valid from active CLK edge

Analog input

tDV

—

AUXPDMn_DOUT hold from active CLK edge

Analog input

tHO

0—

—

AUXPDMn_DOUT propagation delay 2

Digital input

tDD

—

AUXPDMn_CLK propagation delay 4

4.In Slave Mode, CLK propagation delay is measured from a rising/falling edge on AUXPDMn_CLK to the corresponding edge at INn_PDMCLK.

Digital input

tCD

—

(PDM data)

AUXPDMn_DOUT

(output)

VOL

VOH

AUXPDMn_CLK

(Master output/

Slave input)

tCY

tDV

tHO

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