CS48L32 datasheet(92/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

4.5 DSP Peripheral Control

The timer control registers are described in Table 4-32.

Table 4-32. General-Purpose Timer (TIMERn) Control

Bit

Label

Default

Description

Timer 1 Base Address = R1146880 (0x118000)

Timer 2 Base Address = R1147136 (0x118100)

base address

TIMERn_CONTROL

TIMERn_CONT

Timer Continuous Mode select

0 = Single mode

1 = Continuous mode

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

TIMERn_DIR

Timer Count Direction

0 = Down

1 = Up

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

18:16 TIMERn_

PRESCALE[2:0]

000

Timer Count Rate Prescale

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

14:12 TIMERn_

REFCLK_DIV[2:0]

000

Timer Reference Clock Divide (Not valid if TIMERn_REFCLK_SRC = 0x0).

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

If SYSCLK is enabled, and is not selected as clock source, the output frequency

from this divider must be

 SYSCLK / 3, and  12 MHz.

If SYSCLK is disabled, the output of this divider is used as clock reference for the

event logger. In this case, the divider output corresponds to the frequency of event

logging opportunities on the respective modules.

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field.

10:8 TIMERn_

REFCLK_FREQ_

SEL[2:0]

000

Timer Reference Frequency Select (valid if TIMERn_REFCLK_SRC = 0x8)

000 = 6.144 MHz (5.6448 MHz)

001 = 12.288 MHz (11.2896 MHz)

010 = 24.576 MHz (22.5792 MHz)

011 = 49.152 MHz (45.1584 MHz)

All other codes are reserved.

The selected frequency must be less than or equal to the frequency of the source.

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field.

3:0

TIMERn_

REFCLK_

SRC[3:0]

0x0

Timer Reference Source Select.

Timer must be stopped (TIMERn_RUNNING_STS=0) when updating this field.

0x0 = SYSCLK

0x1 = 32 kHz clock

0x4 = MCLK1

0x8 = SYSCLK

0xC = GPIO1

0xD = GPIO2

0xE = GPIO3

0xF = GPIO4

All other codes are

reserved.

base address + 0x04

TIMERn_COUNT_

PRESET

31:0 TIMERn_MAX_

COUNT[31:0]

0x0000

_0000

Timer Maximum Count.

Final count value (when counting up). Starting count value (when counting down).

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field.

base address + 0x0C

TIMERn_START_

AND_STOP

4TIMERn_STOP

Timer Stop Control

Write 1 to stop.

0TIMERn_START

Timer Start Control

Write 1 to start.

If the timer is already running, it restarts from its initial value.

base address + 0x10

TIMERn_STATUS

0TIMERn_

RUNNING_STS

Timer Running Status

0 = Timer stopped

1 = Timer running

CS48L32 Datasheet(PDF) 92 Page - Cirrus Logic

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