CS48L32 datasheet(12/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-10. Miscellaneous Characteristics

Test conditions (unless specified otherwise): VDD_IO = VDD_CP = VDD_A = 1.8 V, VDD_D = VDD_FLL = 1.2 V, VOUT_MIC = 3.1 V (powered from

internal LDO); TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.

Parameter

Min

Typ

Max

Units

Microphone bias

(MICBIAS1x) 1

1.No capacitor on MICBIAS1x. In Regulator Mode, it is required that VVOUT_MIC – VMICBIAS > 200 mV.

Minimum bias voltage 2

Maximum bias voltage

Bias voltage output step size

Bias voltage accuracy

2.Regulator Mode (MICB1_BYPASS = 0), Load current

 1.0 mA.

–5%

0.05

–5%

1.5

2.8

0.1

—

+5%

0.15

+5%

Bias current 3

3.Bias current and load capacitance specifications are for the MICBIAS1 generator (i.e., total current/capacitance across all MICBIAS1x outputs).

Regulator Mode (MICB1_BYPASS = 0), VVOUT_MIC – VMICBIAS >200 mV

Bypass Mode (MICB1_BYPASS = 1)

—

2.4

5.0

Output noise density

Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,

Load current = 1 mA, measured at 1 kHz

—50

—

nV/

Hz

Integrated noise voltage

Regulator Mode (MICB1_BYPASS = 0), MICB1_LVL = 0x4,

Load current = 1 mA, 100 Hz to 7 kHz, A-weighted

—3

—

VRMS

PSRR (VDD_IO, VDD_CP, VDD_A),

defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

PSRR (VDD_D, VDD_FLL),

defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

100

—

Load capacitance 3

Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 0

Regulator Mode (MICB1_BYPASS = 0), MICB1_EXT_CAP = 1

—

0.1

—

1.0

F

Output discharge resistance

MICB1x_EN = 0, MICB1x_DISCH = 1 1.8

2.4



VOUT_MIC

Charge Pump

and Regulator

(CP2 and LDO2)

Output voltage

0.9

—

3.3

Programmable output voltage step size

LDO2_VSEL = 0x00–0x14 (0.9–1.4V )

LDO2_VSEL = 0x14 to 0x27 (1.4 V–3.3 V)

—

100

—

Output current

——

Start-up time

4.7

F on VOUT_MIC —

1.0

2.5

Frequency-Lock

ed Loop (FLL1)

Output frequency

—

MHz

Lock Time

FREF =32kHz, FFLL = 49.152 MHz

FREF =12MHz, FFLL = 49.152 MHz

—

RESET pin input RESET input pulse width 4

4.To trigger a hardware reset, the RESET input must be asserted for longer than this duration.

1—

—

s

Table 3-11. Device Reset Thresholds

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Symbol

Minimum

Typical

Maximum

Units

VDD_A reset threshold

VVDD_A rising

VVDD_A falling

VVDD_A

—

1.06

—

1.66

1.44

VDD_D reset threshold

VVDD_D rising

VVDD_D falling

VVDD_D

—

0.41

—

1.04

0.70

VDD_IO reset threshold

VVDD_IO rising

VVDD_IO falling

VVDD_IO

—

1.06

—

1.66

1.44

Note: The reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured

outside the voltage ranges defined in Table 3-3.

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