CS48L32 datasheet(19/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-19. Master Interface Timing (SPI2 Master)

The following timing information is valid across the full range of recommended operating conditions.

Parameter 1

1.Master interface (SPI2) timing

Symbol

Min

Typ

Max

Units

SS falling edge to SCK rising edge

tSSU

5—

—

SCK falling edge to SS rising edge

tSHO

15.3

—

SCK pulse cycle time

tSCY

—

SCK pulse width low

tSCL

—

SCK pulse width high

tSCH

—

SIOn (input) to SCK set-up time

tDSU

10.35

—

SIOn (input) to SCK hold time

tDHO

0—

—

SIOn (output) valid from falling SCK edge

SCLK slew (90%–10%) = 5 ns, CLOAD (SIOn)= 25 pF

tDV

—

18.3

SIOn (output) hold from falling SCK edge

SCLK slew (90%–10%) = 5 ns, CLOAD (SIOn)= 25 pF

tHO

–3

—

(output)

SCK

(output)

tSSU

tSHO

SIOn

(output)

tSCH

tSCL

tSCY

tDV

tHO

SIOn

(input)

tDHO

tDSU

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