CS48L32 datasheet(18/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-18. Control Interface Timing (SPI1 Slave)

The following timing information is valid across the full range of recommended operating conditions.

Parameter 1

1.Control interface timing

Symbol

Min

Typ

Max

Units

SS falling edge to SCK rising edge

tSSU

2.6

—

SCK falling edge to SS rising edge

tSHO

0—

—

SCK pulse cycle time

SYSCLK disabled (SYSCLK_EN = 0)

SYSCLK_EN = 1, SYSCLK_FREQ = 000

SYSCLK_EN = 1, SYSCLK_FREQ > 000

tSCY

38.4

—

SCK pulse-width low

tSCL

9—

—

SCK pulse-width high

tSCH

9—

—

SCK falling edge to MISO transition

MISO driven on SCK falling edge (SPI1_DPHA = 0)

SCK slew (90%–10%) = 5 ns, CLOAD (MISO) = 10 pF

tDL

—

SCK rising edge to MISO transition

MISO driven on SCK rising edge (SPI1_DPHA = 1)

SCK slew (10%–90%) = 5 ns, CLOAD (MISO) = 10 pF

tDL

—

MOSI to SCK set-up time

tDSU

1.5

—

MOSI to SCK hold time

tDHO

1.7

—

(input)

SCK

(input)

tSSU

tSHO

MOSI

(input)

MISO output

(driven on falling SCK edge)

tSCH

tSCL

tSCY

tDL

tDHO

tDSU

MISO output

(driven on rising SCK edge)

tDL

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