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CS48L32 Datasheet(PDF) 71 Page - Cirrus Logic |
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CS48L32 Datasheet(HTML) 71 Page - Cirrus Logic |
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71 / 192 page  DS1219F4 Cirrus Logic 71 CS48L32 4.3 Digital Core The full list of digital mixer control registers (0x8080–0x907C) is provided in Section 6. Generic register field definitions are provided in Table 4-10. The x_SRC fields select the input sources for the respective ISRC processing blocks. Note that the selected input sources must be configured for the same sample rate as the ISRC to which they are connected. The hexadecimal numbers in Fig. 4-27 indicate the corresponding x_SRC setting for selection of that signal as an input to another digital-core function. The fields associated with the ISRCs are described in Table 4-22. Table 4-22. Digital-Core ISRC Control Register Address Bit Label Default Description R41984 (0xA400) ISRC1_ CONTROL1 31:27 ISRC1_FSL[4:0] 0x00 ISRC1 Low Sample Rate (Sets the lower of the ISRC1 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x03 = SAMPLE_RATE_4 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All ISRC1_INTn_SRC fields must be cleared before changing ISRC1_FSL. 15:11 ISRC1_FSH[4:0] 0x00 ISRC1 High Sample Rate (Sets the higher of the ISRC1 sample rates) 0x00 = SAMPLE_RATE_1 0x01 = SAMPLE_RATE_2 0x02 = SAMPLE_RATE_3 0x03 = SAMPLE_RATE_4 All other codes are reserved. The selected sample rate is valid in the range 8–192 kHz. All ISRC1_DECn_SRC fields must be cleared before changing ISRC1_FSH. R41988 (0xA404) ISRC1_ CONTROL2 11 ISRC1_INT4_EN 0 ISRC1 INT4 Enable Interpolation Channel 4 path from ISRC1_FSL rate to ISRC1_FSH rate 0 = Disabled, 1 = Enabled 10 ISRC1_INT3_EN 0 ISRC1 INT3 Enable Interpolation Channel 3 path from ISRC1_FSL rate to ISRC1_FSH rate 0 = Disabled, 1 = Enabled 9 ISRC1_INT2_EN 0 ISRC1 INT2 Enable Interpolation Channel 2 path from ISRC1_FSL rate to ISRC1_FSH rate 0 = Disabled, 1 = Enabled 8 ISRC1_INT1_EN 0 ISRC1 INT1 Enable Interpolation Channel 1 path from ISRC1_FSL rate to ISRC1_FSH rate 0 = Disabled, 1 = Enabled 3 ISRC1_DEC4_EN 0 ISRC1 DEC4 Enable Decimation Channel 4 path from ISRC1_FSH rate to ISRC1_FSL rate 0 = Disabled, 1 = Enabled 2 ISRC1_DEC3_EN 0 ISRC1 DEC3 Enable Decimation Channel 3 path from ISRC1_FSH rate to ISRC1_FSL rate 0 = Disabled, 1 = Enabled 1 ISRC1_DEC2_EN 0 ISRC1 DEC2 Enable Decimation Channel 2 path from ISRC1_FSH rate to ISRC1_FSL rate 0 = Disabled, 1 = Enabled 0 ISRC1_DEC1_EN 0 ISRC1 DEC1 Enable Decimation Channel 1 path from ISRC1_FSH rate to ISRC1_FSL rate 0 = Disabled, 1 = Enabled |
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