S75WS256NDFBAWMB datasheet(42/216 Pages) SPANSION

42 / 216 page

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

8.5.4

Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by Table 13.1. These commands invoke the

Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all

zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip

contain FFFFh. The system is not required to provide any controls or timings during these oper-

ations. Table 13.1 and Table 13.2 in the appendix show the address and data requirements for

the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-

dresses are no longer latched. The system can determine the status of the erase operation by

using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hard-

ware reset immediately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once that bank has returned to reading array data, to ensure data

integrity.

The following is a C source code example of using the chip erase function. Refer to the Span-

sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for

general information on Spansion Flash memory software development guidelines.

/* Example: Chip Erase Command */

/* Note: Cannot be suspended

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

/* write unlock cycle 1

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

/* write unlock cycle 2

*( (UINT16 *)base_addr + 0x555 ) = 0x0080;

/* write setup command

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;

/* write additional unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;

/* write additional unlock cycle 2 */

*( (UINT16 *)base_addr + 0x000 ) = 0x0010;

/* write chip erase command

8.5.5

Erase Suspend/Erase Resume Commands

When the Erase Suspend command is written during the sector erase time-out, the device imme-

diately terminates the time-out period and suspends the erase operation. The Erase Suspend

command allows the system to interrupt a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. The bank address is required when writing

this command. This command is valid only during the sector erase operation, including the min-

imum tSEA time-out period during the sector erase command sequence. The Erase Suspend

command is ignored if written during the chip erase operation.

When the Erase Suspend command is written after the tSEA time-out period has expired and dur-

ing the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to

suspend the erase operation.

Software Functions and Sample Code

Table 8.15 Chip Erase

(LLD Function = lld_ChipEraseCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Setup Command

Write

Base + AAAh

Base + 555h

0080h

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Chip Erase Command

Write

Base + AAAh

Base + 555h

0010h

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