S75WS256NDFBAWMB datasheet(12/216 Pages) SPANSION

12 / 216 page

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Figure 25.11 Synchronous Program Operation Timings: CLK Latched Addresses ......................................................... 137

Figure 25.12 Accelerated Unlock Bypass Programming Timing ................................................................................. 137

Figure 25.13 Data# Polling Timings (During Embedded Algorithm) ........................................................................... 138

Figure 25.14 Toggle Bit Timings (During Embedded Algorithm) ................................................................................ 138

Figure 25.15 Synchronous Data Polling Timings/Toggle Bit Timings .......................................................................... 139

Figure 25.16 DQ2 vs. DQ6 .................................................................................................................................. 139

Figure 25.17 Latency with Boundary Crossing........................................................................................................ 140

Figure 25.18 Example of Wait States Insertion ...................................................................................................... 140

Figure 25.19 Back-to-Back Read/Write Cycle Timings ............................................................................................. 141

Figure 27.1

Functional Block Diagram ................................................................................................................. 144

Figure 28.2

Power-Up Initialization Timing........................................................................................................... 148

Figure 29.1

Read Operation (ADV# Low)............................................................................................................. 149

Figure 29.2

Write Operation (ADV# Low) ............................................................................................................ 150

Figure 29.3

Page Mode Read Operation (ADV# Low)............................................................................................. 151

Figure 29.4

Burst Mode Read (4-word burst) ....................................................................................................... 152

Figure 29.5

Burst Mode Write (4-word burst)....................................................................................................... 152

Figure 29.6

Wired or Wait Configuration.............................................................................................................. 153

Figure 29.7

Refresh Collision During Read Operation............................................................................................. 154

Figure 29.8

Refresh Collision During Write Operation ............................................................................................ 155

Figure 31.1

Configuration Register Write, Asynchronous Mode Followed by Read ...................................................... 158

Figure 31.2

Configuration Register Write, Synchronous Mode Followed by Read0 ...................................................... 159

Figure 31.3

Wait Configuration (BCR[8] = 0) ....................................................................................................... 162

Figure 31.4

Wait Configuration (BCR[8] = 1) ....................................................................................................... 162

Figure 31.5

Wait Configuration During Burst Operation ......................................................................................... 163

Figure 31.6

Latency Counter (Variable Initial Latency, No Refresh Collision)............................................................. 163

Figure 34.1

AC Input/Output Reference Waveform ............................................................................................... 170

Figure 34.2

Output Load Circuit ......................................................................................................................... 170

Figure 34.3

Initialization Period.......................................................................................................................... 174

Figure 34.4

Asynchronous Read ......................................................................................................................... 175

Figure 34.5

Asynchronous Read Using ADV# ....................................................................................................... 177

Figure 34.6

Page Mode Read ............................................................................................................................. 179

Figure 34.7

Single-Access Burst Read Operation—Variable Latency......................................................................... 181

Figure 34.8

Four-word Burst Read Operation—Variable Latency.............................................................................. 183

Figure 34.9

Four-word Burst Read Operation (with LB#/UB#) ................................................................................ 185

Figure 34.10 Refresh Collision During Write Operation ............................................................................................ 187

Figure 34.9. Continuous Burst Read Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition..................... 188

Figure 34.11 CE#-Controlled Asynchronous Write .................................................................................................. 189

Figure 34.12 LB#/UB#-Controlled Asynchronous Write ........................................................................................... 191

Figure 34.13 WE#-Controlled Asynchronous Write.................................................................................................. 193

Figure 34.14 Asynchronous Write Using ADV#....................................................................................................... 195

Figure 34.15 Burst Write Operation ...................................................................................................................... 197

Figure 34.16 Continuous Burst Write Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition .................... 198

Figure 34.17 Burst Write Followed by Burst Read ................................................................................................... 199

Figure 34.18 Asynchronous Write Followed by Burst Read ....................................................................................... 200

Figure 34.19 Asynchronous Write (ADV# Low) Followed By Burst Read ..................................................................... 202

Figure 34.23. Burst Read Followed by Asynchronous Write (WE#-Controlled).............................................................. 204

Figure 34.26. Burst Read Followed by Asynchronous Write Using ADV# ..................................................................... 206

Figure 34.29. Asynchronous Write Followed by Asynchronous Read—ADV# Low..........................................................208

Figure 34.32. Asynchronous Write Followed by Asynchronous Read ........................................................................... 210

Figure 35.1

Extended Timing for tCEM............................................................................................................................................... 212

Figure 35.2

Extended Timing for tTM................................................................................................................................................. 212

Figure 35.3

Extended Write Operation ................................................................................................................ 213

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