S75WS256NDFBAWMB datasheet(63/216 Pages) SPANSION

63 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

Advance

Information

10 Power Conservation Modes

10.1

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby

mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input. The device enters the CMOS standby mode

when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard

access time (tCE) for read access, before it is ready to read data. If the device is deselected during

erasure or programming, the device draws active current until the operation is completed. ICC3 in

DC Characteristics represents the standby current specification

10.2 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous

mode. the device automatically enables this mode when addresses remain stable for tACC + 20

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when addresses are changed. While in sleep mode,

output data is latched and always available to the system. While in synchronous mode, the auto-

matic sleep mode is disabled. Note that a new burst operation is required to provide new data.

ICC6 in DC Characteristics represents the automatic sleep mode current specification.

10.3 Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of tRP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state

machine to reading array data. The operation that was interrupted should be reinitiated once the

device is ready to accept another command sequence to ensure data integrity.

When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET#

is held at VIL but not within VSS ± 0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the

Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

10.4 Output Disable (OE#)

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the

high impedance state.

S75WS256NDFBAWMB Datasheet(PDF) 63 Page - SPANSION