S75WS256NDFBAWMB datasheet(25/216 Pages) SPANSION

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February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

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Information

8 Device Operations

This section describes the read, program, erase, simultaneous read/write operations, handshak-

ing, and reset features of the Flash devices.

Operations are initiated by writing specific commands or a sequence with specific address and

data patterns into the command registers (see Table 13.1 and Table 13.2). The command register

itself does not occupy any addressable memory location; rather, it is composed of latches that

store the commands, along with the address and data information needed to execute the com-

mand. The contents of the register serve as input to the internal state machine and the state

machine outputs dictate the function of the device. Writing incorrect address and data values or

writing them in an improper sequence may place the device in an unknown state, in which case

the system must write the reset command to return the device to the reading array data mode.

8.1

Device Operation Table

The device must be setup appropriately for each operation. Table 8.1 describes the required state

of each control pin for any particular operation.

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.

8.2

Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data

is read from one memory location at a time. Addresses are presented to the device in random

order, and the propagation delay through the device causes the data on its outputs to arrive asyn-

chronously with the address on its inputs.

The device defaults to reading array data asynchronously after device power-up or hardware re-

set. Asynchronous read requires that the CLK signal remain at VIL during the entire memory read

operation. To read data from the memory array, the system must first assert a valid address on

Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD#

latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH.

Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling

edge of OE#.

Table 8.1 Device Operations

Operation

CE#

OE#

WE#

Addresses

DQ15–0

RESET#

CLK

AVD#

Asynchronous Read - Addresses Latched

Addr In

Data Out

Asynchronous Read - Addresses Steady State

Addr In

Data Out

Asynchronous Write

Addr In

I/O

Synchronous Write

Addr In

I/O

Standby (CE#)

HIGH Z

Hardware Reset

HIGH Z

Burst Read Operations (Synchronous)

Load Starting Burst Address

Addr In

Advance Burst to next address with appropriate Data

presented on the Data Bus

Burst

Data Out

Terminate current Burst read cycle

HIGH Z

Terminate current Burst read cycle via RESET#

HIGH Z

Terminate current Burst read cycle and start new Burst

read cycle

Addr In

I/O

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