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S75WS256NDFBAWMB Datasheet(PDF) 85 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 85 Page - SPANSION |
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85 / 216 page  February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 83 Advance Information Note: Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check- ing the status of the program or erase operation in the busy bank. The system should read status twice to ensure valid information. Figure 12.24 Back-to-Back Read/Write Cycle Timings OE# CE# WE# tOEH Data Addresses AVD# PD/30h AAh RA PA/SA tWC tDS tDH tRC tRC tOE tAS tAH tACC tOEH tWP tGHWL tOEZ tWC tSR/W Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence RD RA 555h RD tWPH |
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