S75WS256NDFBAWMB datasheet(47/216 Pages) SPANSION

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February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

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Information

quence. Note that the Data# Polling is valid only for the last word being programmed in the write-

buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other

than the last word to be programmed in the write-buffer-page returns false status information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.

When the Embedded Program algorithm is complete, the device outputs the datum programmed

to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-

mately tPSP, then that bank returns to the read mode.

During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded

Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro-

duces a 1 on DQ7. The system must provide an address within any of the sectors selected for

erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode.

If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7

at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-

chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may

change from providing status information to valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device has completed

the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be

still invalid. Valid data on DQ7-D00 appears on successive read cycles.

See the following for more information: Table 8.23, Write Operation Status, shows the outputs

for Data# Polling on DQ7. Figure 8.6, Write Operation Status Flowchart, shows the Data# Polling

algorithm; and Figure 12.17, Data# Polling Timings (During Embedded Algorithm), shows the

Data# Polling timing diagram.

S75WS256NDFBAWMB Datasheet(PDF) 47 Page - SPANSION