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S75WS256NDFBAWMB Datasheet(PDF) 45 Page - SPANSION

Part # S75WS256NDFBAWMB
Description  Stacked Multi-Chip Product (MCP)
PDF  216 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S75WS256NDFBAWMB Datasheet(HTML) 45 Page - SPANSION

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February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
43
Advance
Information
If the system asserts VHH on this input, the device automatically enters the aforementioned Un-
lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used
to reset the device. Removing VHH from the ACC input, upon completion of the embedded pro-
gram or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH.
The ACC pin must not be at VHH for operations other than accelerated programming and ac-
celerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may
result.
ACC locks all sector if set to VIL. ACC should be set to VIH for all other conditions.
8.5.8
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. See the Appendix for the requirements for
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.



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