S75WS256NDFBAWMB datasheet(82/216 Pages) SPANSION

82 / 216 page

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Notes:

1. RDY(1) active with data (D8 = 1 in the Configuration Register).

2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. Figure shows the device not crossing a bank in the process of performing an erase or program.

5. RDY does not go low and no additional wait states are required if the Burst frequency is <=66 MHz and the Boundary

Crossing bit (D14) in the Configuration Register is set to 0

Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz

CLK

Address (hex)

C124

C125

C126

C127

C128

C129

C130

C131

D124

D125

D126

D127

D128

D129

D130

(stays high)

AVD#

RDY(1)

Data

OE#,

CE#

(stays low)

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

latency

RDY(2)

latency

tRACC

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