S75WS256NDFBAWMB datasheet(52/216 Pages) SPANSION

52 / 216 page

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

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Inf o rmation

8.9

Hardware Reset

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of tRP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state

machine to reading array data.

To ensure data integrity the operation that was interrupted should be reinitiated once the device

is ready to accept another command sequence.

When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL, but not at VSS, the standby current is greater.

RESET# may be tied to the system reset circuitry which enables the system to read the boot-up

firmware from the Flash memory upon a system reset.

See Figures 12.5 and 12.12 for timing diagrams.

8.10 Software Reset

Software reset is part of the command set (see Table 13.1) that also returns the device to array

read mode and must be used for the following conditions:

to exit Autoselect mode

when DQ5 goes high during write status operation that indicates program or erase cycle was

not successfully completed

exit sector lock/unlock operation.

to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.

after any aborted operations

Note: Base = Base Address.

The following is a C source code example of using the reset function. Refer to the Spansion

Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general

information on Spansion Flash memory software development guidelines.

/* Example: Reset (software reset of Flash state machine) */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

The following are additional points to consider when using the reset command:

This command resets the banks to the read and address bits are ignored.

Reset commands are ignored once erasure has begun until the operation is complete.

Once programming begins, the device ignores reset commands until the operation is com-

plete

The reset command may be written between the cycles in a program command sequence be-

fore programming begins (prior to the third cycle). This resets the bank to which the system

was writing to the read mode.

Software Functions and Sample Code

Table 8.24 Reset

(LLD Function = lld_ResetCmd)

Cycle

Operation

Byte Address

Word Address

Data

Reset Command

Write

Base + xxxh

00F0h

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