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S75WS256NDFBAWMB Datasheet(PDF) 62 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 62 Page - SPANSION |
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62 / 216 page  60 S75WS256Nxx Based MCPs S75WS-N-00_A0 February 17, 2005 Ad van c e Inf o rmation The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. 9.7.4 Write Pulse Glitch Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 9.7.5 Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com- mands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. |
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