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S75WS256NDFBAWMB Datasheet(PDF) 73 Page - SPANSION |
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S75WS256NDFBAWMB Datasheet(HTML) 73 Page - SPANSION |
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73 / 216 page  February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 71 Advance Information Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode with wrap around. 4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (0-F). Figure 12.8 8-word Linear Burst with Wrap Around Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at address + 1 , address + 2, or address + 3, additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in asynchronous mode with out wrap around. 4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 1st address in range (c-13). Figure 12.9 8-word Linear Burst without Wrap Around DC DD OE# Data Addresses Ac AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tIACC tAOE tBDH DE DF DB 7 cycles for initial access shown. Hi-Z tRACC 12 3 4 5 6 7 tRDYS tBACC tCR D8 tRACC DC DD OE# Data Addresses Ac AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tIACC tBDH DE DF D13 Hi-Z tRACC 12 3 4 5 6 7 tRDYS tBACC tCR D10 tRACC tAOE 7 cycles for initial access shown. |
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