S75WS256NDFBAWMB datasheet(11/216 Pages) SPANSION

11 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

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Information

Figures

Figure 5.1

Connection Diagram – Cellular Ram-Based 84-ball Fine-Pitch Ball Grid Array.............................................15

Figure 5.2

Look Ahead Pinout – 1.8 V only x 16NOR + x16pSRAM + x16MirrorBit Data..............................................16

Figure 8.1

Synchronous/Asynchronous State Diagram...........................................................................................24

Figure 8.2

Synchronous Read ............................................................................................................................27

Figure 8.3

Single Word Program.........................................................................................................................33

Figure 8.4

Write Buffer Programming Operation ...................................................................................................37

Figure 8.5

Sector Erase Operation ......................................................................................................................39

Figure 8.6

Write Operation Status Flowchart ........................................................................................................46

Figure 9.1

Advanced Sector Protection/Unprotection .............................................................................................52

Figure 9.2

PPB Program/Erase Algorithm .............................................................................................................55

Figure 9.3

Lock Register Program Algorithm.........................................................................................................58

Figure 12.1

Maximum Negative Overshoot Waveform .............................................................................................65

Figure 12.2

Maximum Positive Overshoot Waveform...............................................................................................65

Figure 12.3

Test Setup .......................................................................................................................................66

Figure 12.4

Input Waveforms and Measurement Levels...........................................................................................66

Figure 12.5

VCC Power-up Diagram ......................................................................................................................67

Figure 12.6

CLK Characterization .........................................................................................................................69

Figure 12.7

CLK Synchronous Burst Mode Read......................................................................................................70

Figure 12.8

8-word Linear Burst with Wrap Around.................................................................................................71

Figure 12.9

8-word Linear Burst without Wrap Around ............................................................................................71

Figure 12.10 Linear Burst with RDY Set One Cycle Before Data ..................................................................................72

Figure 12.11 Asynchronous Mode Read...................................................................................................................73

Figure 12.12 Reset Timings...................................................................................................................................73

Figure 12.13 Chip/Sector Erase Operation Timings ...................................................................................................75

Figure 12.14 Asynchronous Program Operation Timings ............................................................................................76

Figure 12.15 Synchronous Program Operation Timings .............................................................................................77

Figure 12.16 Accelerated Unlock Bypass Programming Timing ...................................................................................77

Figure 12.17 Data# Polling Timings (During Embedded Algorithm) .............................................................................78

Figure 12.18 Toggle Bit Timings (During Embedded Algorithm) ..................................................................................78

Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................79

Figure 12.20 DQ2 vs. DQ6 ....................................................................................................................................79

Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................80

Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank ......................................................................81

Figure 12.23 Example of Wait State Insertion ..........................................................................................................82

Figure 12.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................83

Figure 19.1

Synchronous/Asynchronous State Diagram......................................................................................... 110

Figure 19.2

Program Word Operation.................................................................................................................. 115

Figure 19.3

Write Buffer Programming Operation ................................................................................................. 116

Figure 20.4

Erase Operation .............................................................................................................................. 119

Figure 22.5

Data# Polling Algorithm ................................................................................................................... 122

Figure 22.6

Toggle Bit Algorithm........................................................................................................................ 123

Figure 22.7

Maximum Positive Overshoot Waveform............................................................................................. 125

Figure 24.1

Test Setup ..................................................................................................................................... 127

Figure 24.2

Input Waveforms and Measurement Levels......................................................................................... 127

Figure 25.1

VCC Power-up Diagram .................................................................................................................... 128

Figure 25.2

CLK Characterization ....................................................................................................................... 128

Figure 25.3

CLK Synchronous Burst Mode Read.................................................................................................... 130

Figure 25.4

8-word Linear Burst with Wrap Around............................................................................................... 131

Figure 25.5

8-word Linear Burst without Wrap Around .......................................................................................... 131

Figure 25.6

Burst with RDY Set One Cycle Before Data.......................................................................................... 132

Figure 25.7

Asynchronous Mode Read with Latched Addresses ............................................................................... 133

Figure 25.8

Asynchronous Mode Read................................................................................................................. 133

Figure 25.9

Reset Timings................................................................................................................................. 134

Figure 25.10 Asynchronous Program Operation Timings: WE# Latched Addresses ...................................................... 136

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