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TMP89FS60 Datasheet(PDF) 245 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 245 Page - Toshiba Semiconductor |
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245 / 410 page ![]() Page 231 TMP89FS60 RA001 16.12.5 Transmit busy flag If transmission is completed with no waiting data in TD0BUF (when UART0SR<TBFL>="0"), UART0SR<TBSY> is cleared to "0". When transmission is restarted after data is written into TD0BUF, UART0SR<TBSY> is set to "1". At this time, an INTTXD0 interrupt request is generated. Figure 16-16 Transmit Busy Flag and Occurrence of Transmit Buffer Full 16.12.6Transmit Buffer Full When TD0BUF has no data, or when data in TD0BUF is transferred to the transmit shift register and trans- mission is started, UART0SR<TBFL> is cleared to "0". At this time, an INTTXD0 interrupt request is gener- ated. Writing data into TD0BUF sets UART0SR<TBFL> to "1". Figure 16-17 Occurrence of Transmit Buffer Full TXD0 pin input INTTXD0 interrupt request UART0SR<TBFL> Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Start Bit0 Bit1 Bit6 Bit7 Stop Writing of TD0BUF UART0SR<TBSY> UART0CR1<TXE> Data A Data B Writing of data A Writing of data B TXD0 pin input INTTXD0 interrupt request UART0SR<TBFL> Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Start Bit0 Bit1 Bit2 Bit3 Bit6 Bit7 Stop Writing of TD0BUF UART0SR<TBSY> UART0CR1<TXE> Data A Data B Writing of data A Writing of data B |
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