TMP89FS60 datasheet(273/410 Pages) TOSHIBA

273 / 410 page

Page 259

TMP89FS60

RA001

17.6 AC Characteristics

Figure 17-16 AC Characteristics

Figure 17-17 Interval time between bytes

(VSS = 0 V, VDD = 4.5 V - 5.5 V, Topr = -40 to 85°C)

Parameter

Symbol

Condition

Min

Typ.

Max

Unit

SCLK cycle time

tSCY

Internal clock operation

SO pin and SCLK pin load capacity=100 pF

2 / fcgck

SCLK "L" pulse width

tSCYL

1 / fcgck

− 25

SCLK "H" pulse width

tSCYH

1 / fcgck

− 15

SI input setup time

tSIS

SI input hold time

tSIH

SO output delay time

tSOD

−50

-50

SCLK cycle time

tSCY

External clock operation

SO pin and SCLK pin load capacity=100 pF

2 / fcgck

SCLK "L" pulse width

tSCYL

1 / fcgck

SCLK "H" pulse width

tSCYH

1 / fcgck

SI input setup time

tSIS

SI input hold time

tSIH

SO output delay time

tSOD

SCLK low-level input voltage

tSCLKL

VDD × 0.30

SCLK high-level input voltage

tSCLKH

VDD × 0.70

VDD

SCLK pin

tSIS

VSCLKL

VSCLKH

tSCYL

tSCYH

tSCY

tSOD

tSIH

SI pin

SO pin

tBI

Leading edge at the

1st bit (transmit edge)

Trailing edge at the

8th bit (receive edge)

SCLK0 pin

SO0 pin

SI0 pin

Symbol

Name

Minimum time

tBI

Interval time between bytes

4/fcgck

TMP89FS60 Datasheet(PDF) 273 Page - Toshiba Semiconductor

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