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TMP89FS60 Datasheet(PDF) 310 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 310 Page - Toshiba Semiconductor |
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310 / 410 page  Page 296 20. 10-bit AD Converter (ADC) 20.2 Control TMP89FS60 RA001 Note 1: Make sure that you make the ACK setting when AD conversion is in a halt condition (ADCCR2<ADBF>="0"). Note 2: Make sure that you write "0" to bit 3 of ADCCR2. Note 3: If STOP, IDLE0 or SLOW mode is started, EOCF and ADBF are initialized to "0". Note 4: If the AD converted value register (ADCDRH) is read, EOCF is cleared to "0". It is also cleared to "0" if AD conversion is started (ADCCR1<ADRS>="1") without reading ADCDRH after completing AD conversion in single mode. Note 5: If an instruction to read ADCCR2 is executed, 0 is read from bits 3 through 5. AD converter control register 2 ADCCR2 76543 210 (0x0035) Bit Symbol EOCF ADBF - - "0" ACK Read/Write RRRR W R/W After reset 00000 000 EOCF AD conversion end flag 0: 1: Before conversion or during conversion Conversion end ADBF AD conversion BUSY flag 0: 1: AD conversion being halted AD conversion being executed ACK AD conversion time select (exam- ples of AD conversion time are shown in the table below) 000: 001: 010: 011: 100: 101: 110: 111: 39/fcgck 78/fcgck 156/fcgck 312/fcgck 624/fcgck 1248/fcgck Reserved Reserved Table 20-1 ACK Settings and Conversion Times Relative to Frequencies Frequency (fcgck) ACK setting Conversion time 8MHz 4MHz 2MHz 5MHz 2.5MHz 1MHz 0.5MHz 0.25 MHz 000 39/fcgck - - 19.5 µs - 15.6 µs 39.0 µs78.0 µs 156.0 µs 001 78/fcgck - 19.5 µs39.0 µs 15.6 µs 31.2 µs 78.0 µs 156.0 µs- 010 156/fcgck 19.5 µs39.0 µs78.0 µs 31.2 µs 62.4 µs 156.0 µs- - 011 312/fcgck 39.0 µs78.0 µs 156.0 µs 62.4 µs124.8 µs- - - 100 624/fcgck 78.0 µs 156.0 µs - 124.8 µs --- - 101 1248/fcgck 156.0 µs - ----- - 11* Reserved Note 1: Spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces. fcgck: High Frequency oscillation clock [Hz] Note 2: Above conversion times do not include the time shown below. - Time from when ADCCR1<ADRS> is set to 1 to when AD conversion is started - Time from when AD conversion is finished to when a converted value is stored in ADCDRL and ADCDRH. If ACK = 00*, the longest conversion time is 10/fcgck (s). If ACK = 01*, it is 32/fcgck (s). If ACK = 10*, it is 128/fcgck(s). Note 3: The conversion time must be longer than the following time by analog reference voltage (VAREF). - VAREF = 4.5 to 5.5 V 15.6 µs or longer - VAREF = 2.7 to 5.5 V 31.2 µs or longer - VAREF = 2.5 to 5.5 V 124.8 µs or longer |
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