R34DS0012EU0504 Rev.5.04

Page 26

Sep 18, 2025

ISL73141SEH Datasheet

specifications, the settling time must be met for the input signals on the analog input of the ISL73141SEH. To

accurately resolve to 1 LSB, the settling time is defined by Equation 3:

Simplifying this results in Equation 4:

Solving for t results in:

, which can be written as

and further simplified to

.

Settling time is t, RS ×CP is τ, and the resolution of the ADC is N.

The ISL73141SEH is a 14-bit ADC, which means the settling time to attain 1 LSB accuracy is 9.7 × τ. For

example, the ISL73141SEHEV1Z evaluation board employs a 24Ω resistor for RS and a 470pF capacitor for CP,

which means that the required settling time would be t = 0.693 × 14 × 24Ω × 470pF = 109.4ns. If different RS and

CP values are used, calculate the settling time for those conditions. These calculations assume the settling time of

the input network RS and CP are much larger than the settling time of any amplifier driving the ISL73141SEH

analog input. If this is not the case, the settling time of the input network must be root-sum-squared with the

settling time of the amplifier to determine the required settling time using Equation 5:

6.

Die and Assembly Characteristics

(EQ. 3)

(EQ. 4)

(EQ. 5)

Table 1.

Die and Assembly Related Information

Die Information

Dimensions

2410µm x 3910µm (95 mils x 154 mils)

Thickness: 483µm ±25µm (19 mils ±1 mil)

Interface Materials

Passivation

Oxide/Nitride Total Thickness 24.5 kÅ

Top Metallization

Top metal/Bond Pad Composition

99.5% Al, 0.5%Cu

Process

0.25um CMOS

Assembly Information

Substrate Potential

GND

Additional Information

Transistor Count

37700

Weight of Packaged Device

0.572 grams (typical) - K14.A package

Lid Characteristics

Finish: Gold

Lid Potential: Connected to package Pin 14 (DGND)

1

2

N

-------

e

t

–





=

2

N



ln

t



--

–

=

t-



2

N



ln



=

tN





2





ln



=

t

0.693 N





=

ttAMP



2

tRC



2

+

=