68HC705BD7 datasheet(44/85 Pages) FREESCALE

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SECTION 7: INPUT/OUTPUT PORTS

Page 34

GENERAL RELEASE SPECIFICATION

MC68HC05BD7 Rev. 2.0

shares its pin with the CLAMP output. See SECTION 10 for the description of CLAMP

signal. It becomes the CLAMP output when the CLAMP bit in SPIOCR register is set. PD3

is a +12V open-drain I/O pin which shares its pin with the SOG input. Also see SECTION

10 for the description of SOG input. It is configured as SOG input when the SOG bit in

SPIOCR register is set. The Port D data register is at $03 and the data direction register

(DDR) is at $07. Reset does not affect the data register, yet clears the data direction

corresponding port bit to output mode.

7.5

Input/Output Programming

Bidirectional port lines may be programmed as an input or an output under software control.

The direction of the pins is determined by the state of the corresponding bit in the port data

direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured

as an output if its corresponding DDR bit is set. A pin is configured as an input if its

corresponding DDR bit is cleared.

During Reset, all DDRs are cleared, which configure all port pins as inputs. The data

direction registers are capable of being written to or read by the processor. During the

programmed output state, a read of the data register actually reads the value of the output

data latch and not the I/O pin. See Figure 7-1 and .

Figure 7-1: Port I/O Circuitry

I/O

Read Data

Write Data

Data

Internal HC05

Data Bus

Reset

(RST)

Read/Write DDR

Data Direction

OUTPUT

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68HC705BD7 Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc