68HC705BD7 datasheet(47/85 Pages) FREESCALE

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SECTION 8: PULSE WIDTH MODULATION

Page 37

MC68HC05BD7 Rev. 2.0

GENERAL RELEASE SPECIFICATION

SECTION 8

PULSE WIDTH MODULATION

There are 16 PWM channels. Channel 0 to channel 7 are dedicated PWM channels with

5V open-drain option. Channel 8 to channel 15 are shared with ports C under the control

of the corresponding configuration register. The channel 8 and channel 9 are 12V open-

drain outputs.

8.1

Operation of 8-Bit PWM

Each 8-Bit PWM channel is composed of an 8-bit register which contains a 5-bit PWM in

MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. There are 16 data

registers as shown in Figure 8-1 located from $20 to $2F. The value programmed in the 5-

bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM

portion is the MCU clock and the repetition rate of the output is hence 62.5 KHz at 2 MHz

MCU clock.

The 3-bit BRM will generate a number of narrow pulses which are equally distributed

among an 8-PWM-cycle frame. The number of pulses generated is equal to the number

programmed in the 3-bit BRM portion. An example of the waveform is shown in Figure 8-2.

Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output

will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and N is the content

of the 3-bit BRM portion. Using this mechanism, a true 8-bit resolution PWM type DAC with

reasonably high repetition rate can be obtained.

Figure 8-1: PWM Data Register

The value of each PWM Data Register is continuously compared with the content of an

internal counter to determine the state of each PWM channel output pin. Double buffering

is not used in this PWM design.

0PWM3

0PWM1

0PWM4

0BRM1

0BRM2

0PWM0

0000000

6543210

0PWM2

PWMR

$20-$2F

reset

⇒

0BRM0

Freescale Semiconductor, Inc.

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